Cirrus Logic CS4382 - Manual (Page 12)

12 DS514F2
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
™
FORMAT
(For KQZ T
A
= -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C
L
= 30 pF)
Notes:
22. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For F
SCK
< 1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
sclk
- MHz
RST Rising Edge to CS Falling t
srs
500 - ns
CCLK Edge to CS Falling (Note 22) t
spi
500 - ns
CS High Time Between Transmissions t
csh
1.0 - µs
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
- ns
CCLK High Time t
sch
- ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 23) t
dh
15 - ns
Rise Time of CCLK and CDIN (Note 24) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 24) t
f2
- 100 ns
MCLK
2
-----------------
1
MCLK
-----------------
1
MCLK
-----------------
t r2 t f2
t dsu t dh
t sch t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs RST
Figure 4. Control Port Timing - SPI Format