Cirrus Logic CS4382 - Manual (Page 28)

28 DS514F2
CS4382
6. APPLICATIONS
6.1 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4382 requires careful attention to power supply and grounding arrange-
ments to optimize performance.
Figures 5 and 6 show the recommended power arrangement with VA, VD, VLS and
VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as pos-
sible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be
placed on each supply pin (see
Section 1. Characteristics and Specifications for recommended voltages).
6.2 PCM Mode Select
The CS4382 operates in one of three PCM oversampling modes based on the input sample rate. Mode se-
lection is determined by the M3 and M2 pins in Stand-Alone Mode or the FM bits in Control Port Mode. Sin-
gle-Speed Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-
Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-
Speed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. The PCM
digital interface format is determined by the M1 and M0 pins in Stand-Alone Mode or the DIF bits in Control
Port Mode.
In Stand-Alone Mode, the states of these pins are continually scanned for changes; however, the mode
should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode
to another.
6.3 Recommended Power-Up Sequence
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and VQ will remain low.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone
power-up sequence. The control port will be accessible at this time. If Control Port operation is desired,
write the CPEN bit prior to the completion of the Stand-Alone power-up sequence, approximately 512
LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles
in Quad-Speed Mode). Writing this bit will halt the Stand-Alone power-up sequence and initialize the
control port to its default settings. The desired register settings can be loaded while keeping the PDN
bit set to 1.
3. If Control Port Mode is selected via the CPEN bit, set the PDN bit to 0 which will initiate the power-up
sequence.
6.4 Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4382 evalua-
tion board, CDB4382, as seen in Figure
42 . The CS4382 does not include phase or amplitude compensa-
tion for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on
the external analog circuitry.
6.5 Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382 incorporates
selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in
each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a va-
riety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the control
port section for more details).