Table 5. common clock frequencies, Table 7. mode selection, stand-alone mode options, Cs4382 – Cirrus Logic CS4382 User Manual
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DS514F2
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CS4382
Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK (MHz)
Control port
only modes
MCLK Ratio
256x
384x
512x
768x*
1024x*
Single-Speed
(4 to 50 kHz)
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
128x
192x
256x
384x
512x*
Double-Speed
(50 to 100 kHz)
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
64x
96x
128x
192x
256x*
Quad-Speed
(100 to 200 kHz)
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Note:
*These modes are only available in Control Port Mode by setting the MCLKDIV bit = 1.
Table 5. Common Clock Frequencies
M1
(DIF1)
M0
(DIF0)
DESCRIPTION
FORMAT
FIGURE
0
0
Left Justified, up to 24-bit data
0
0
1
I²S, up to 24-bit data
1
1
0
Right Justified, 16-bit Data
2
1
1
Right Justified, 24-bit Data
3
Table 6. Digital Interface Format, Stand-Alone Mode Options
M3
M2
(DEM)
DESCRIPTION
0
0
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
0
1
Single-Speed with 44.1 kHz De-Emphasis; see
1
0
Double-Speed (50 to 100 kHz sample rates)
1
1
Quad-Speed (100 to 200 kHz sample rates)
Table 7. Mode Selection, Stand-Alone Mode Options
DSD_Mode
(LRCK1)
M2
M1
M0
DESCRIPTION
1
0
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options