Cirrus Logic CS4382 - Manual (Page 18)

18 DS514F2
CS4382
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins. An additional write of 99h
to register 00h and 80h to register 1Ah is required to access the modes denoted with *.
4.2.2 Serial Audio Data Clock Source (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given SDINx
line. For more details see “Clock Source Selection” on page 29.
4.3 Mode Control 3 (Address 03h)
4.3.1 Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim-
eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
DIF2 DIF1 DIFO DESCRIPTION Note
0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate
0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate *
0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate *
0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate *
1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate
1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate *
1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate *
1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate *
Table 2. Digital Interface Formats - DSD Mode
7 6 5 4 3 2 1 0
SZC1 SZC0 SNGLVOL RMP_UP Reserved AMUTE Reserved MUTEC
1 0 0 0 0 1 0 0