Cirrus Logic CS4382 - Manual (Page 25)

DS514F2 25
CS4382
5. PIN DESCRIPTION
Pin Name # Pin Description
VD 4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.
GND
5
31
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK 6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates
several standard audio sample rates and the required master clock frequency.
LRCK1
LRCK2 7
10
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4 8
11
13
14
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK1
SCLK2 9
12
Serial Clock (Input) - Serial clock for the serial audio interface.
VLC 18
Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.
RST 19
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
FILT+ 20
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
VQ 21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance.
However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and
the DC current is less than the maximum specified in the Analog Characteristics and Specifications sec-
tion.
SD
IN
3
GND
AOUTB2-
AOUTA3+
AOUTB3-
AOUTB2+
VA
AOUTA3-
AOUTB3+
6
2
4
8
10
1
3
5
7
9
11
12
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
31
35
33
29
27
36
34
32
30
28
26
25
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
M CLK
DSDB1
VD
SDIN1
LRCK2
DSDA2
DSDA1
GND
SCLK1
SDIN2
SCLK2
LRCK1(DSD_EN)
M
3
(D
SD
_
SC
L
K)
DS
DB
3
DS
DA
3
DS
DA
4
CS4382
DS
DB
4
VLS
SD
IN
4
M
2
(S
CL
/CCL
K
)
M
1
(S
DA/
CDI
N)
VL
C
RS
T
FI
LT+
VQ
MU
T
E
C
2
3
4
M0
(A
D
0
/C
S
)
AOUTA2+
AOUTA2-
AO
UT
B
1
+
AO
U
T
B1
-
AO
U
T
A1-
AO
U
T
A1
+
DS
DB
2
MU
T
E
C
1
AOUTA4-
AOUTA4+
AO
U
T
B4+
AO
U
T
B4
-