Cirrus Logic CS4382 - Manual (Page 11)

DS514F2 11
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C
®
FORMAT
(For KQZ T
A
= -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C
L
= 30 pF)
Notes:
19. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
21. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
scl
- 100 kHz
RST Rising Edge to Start t
irs
500 - ns
Bus Free Time Between Transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup Time for Repeated Start Condition t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 19) t
hdd
0 - µs
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of SCL and SDA t
rc
, t
rc
- 1 µs
Fall Time SCL and SDA t
fc
, t
fc
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - µs
Acknowledge Delay from SCL Falling (Note 20) t
ack
- (Note 21) ns
15
256 Fs
×
---------------------
15
128 Fs
×
---------------------
15
64 Fs
×
------------------
SDA
SCL
001100
ADDR
AD0
R/W
Start
ACK
DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 3. Control Port Timing - I²C Format