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Register description, 1 mode control 1 (address 01h), 1 control port enable (cpen) – Cirrus Logic CS4382 User Manual

Page 16: 2 freeze controls (freeze), 3 master clock divide enable (mclkdiv), 4 dac pair disable (dacx_dis)

Register description, 1 mode control 1 (address 01h), 1 control port enable (cpen) | 2 freeze controls (freeze), 3 master clock divide enable (mclkdiv), 4 dac pair disable (dacx_dis) | Cirrus Logic CS4382 User Manual | Page 16 / 42 Register description, 1 mode control 1 (address 01h), 1 control port enable (cpen) | 2 freeze controls (freeze), 3 master clock divide enable (mclkdiv), 4 dac pair disable (dacx_dis) | Cirrus Logic CS4382 User Manual | Page 16 / 42