Cirrus Logic CS42L73 - Manual (Page 9)

DS882F1 9
CS42L73
7.3 Layout With Fine-Pitch, Ball-Grid Packages ................................................................................ 125
8. PERFORMANCE DATA ..................................................................................................................... 126
8.1 Analog Input Path Attributes ........................................................................................................ 126
8.1.1 PGA Analog Volume Nonlinearity (DNL and INL) ............................................................... 126
8.2 Analog Mic/Line ADC and Digital Mic Input Path Attributes ......................................................... 127
8.2.1 Input Path Digital LPF Response ........................................................................................ 127
8.2.2 Input Path Digital HPF Response ........................................................................................ 128
8.3 Core Circuitry Attributes ............................................................................................................... 129
8.3.1 ASRC Attributes .................................................................................................................. 129
8.3.1.1 Response ................................................................................................................. 129
8.3.1.2 Group Delay ............................................................................................................. 130
8.3.1.3 Lock Time ................................................................................................................ 130
8.4 Analog Output Paths Attributes .................................................................................................... 131
8.4.1 DAC Digital LPF Response ................................................................................................. 131
8.4.2 DAC HPF Response ........................................................................................................... 132
8.4.3 Output Analog Volume Nonlinearity (DNL and INL) ............................................................ 132
8.4.4 Startup Times ...................................................................................................................... 133
9. PARAMETER DEFINITIONS .............................................................................................................. 134
10. PACKAGE DIMENSIONS ................................................................................................................ 135
10.1 WLCSP Package ....................................................................................................................... 135
10.2 FBGA Package .......................................................................................................................... 136
11. THERMAL CHARACTERISTICS ..................................................................................................... 137
12. ORDERING INFORMATION ............................................................................................................ 137
13. REFERENCES .................................................................................................................................. 137
14. REVISION HISTORY ........................................................................................................................ 138
LIST OF FIGURES
Figure 1.Typical Connection Diagram ....................................................................................................... 17
Figure 2.MICx Dynamic Range Test Configuration ................................................................................... 24
Figure 3.Analog Input CMRR Test Setup .................................................................................................. 24
Figure 4.LINEIN_REF/MICx_REF Input Voltage Test Setup .................................................................... 24
Figure 5.Headphone Output Test Configuration ....................................................................................... 28
Figure 6.Line Output Test Configuration ................................................................................................... 29
Figure 7.Ear Speaker Output Test Configuration ...................................................................................... 30
Figure 8.Speakerphone and Speakerphone Line Output Test Configuration ........................................... 32
Figure 9.Power Consumption Test Configuration ..................................................................................... 34
Figure 10.Power and Reset Sequencing .................................................................................................. 36
Figure 11.Digital Mic Interface Timing ....................................................................................................... 37
Figure 12.Serial Port Interface Timing—I²S Format .................................................................................. 39
Figure 13.Serial Port Interface Timing—PCM Format .............................................................................. 39
Figure 14.I²C Control Port Timing ............................................................................................................. 40
Figure 15.Single-Ended Output Configuration .......................................................................................... 43
Figure 16.Pseudodifferential Output Configuration ................................................................................... 43
Figure 17.Class H Operation ..................................................................................................................... 44
Figure 18.Class H Control - Adapt-to-Volume Mode ................................................................................. 45
Figure 19.VCP_FILT Transitions ............................................................................................................... 47
Figure 20.VCP_FILT Hysteresis ............................................................................................................... 48
Figure 21.Input Power vs. Output Power .................................................................................................. 49
Figure 22.Peak Detect & Limiter ............................................................................................................... 50
Figure 23.HP Short Circuit Setup .............................................................................................................. 51
Figure 24.Line Short Circuit Setup ............................................................................................................ 51
Figure 25.Serial Port Busing when Mastering Timing ............................................................................... 52
Figure 26.Serial Port Busing When Slave Timed ...................................................................................... 52