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53 fast mode 1 (address 7eh), 1 fast mode bits 15:8, 54 fast mode 2 (address 7fh) – Cirrus Logic CS42L73 User Manual

Page 125: 1 fast mode bits 7:0, Pcb layout considerations, 1 power supply, 2 grounding, 3 layout with fine-pitch, ball-grid packages, 1 power supply 7.2 grounding, P 125

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DS882F1

125

CS42L73

6.53 Fast Mode 1 (Address 7Eh)

6.53.1 Fast Mode Bits 15:8

See

“Fast Start Mode” on page 73

.

6.54 Fast Mode 2 (Address 7Fh)

6.54.1 Fast Mode Bits 7:0

See

“Fast Start Mode” on page 73

.

7. PCB LAYOUT CONSIDERATIONS

7.1

Power Supply

As with any high-resolution converter, the CS42L73 requires careful attention to power supply and ground-
ing arrangements for its potential performance to be realized.

Figure 1 on page 17

shows the recommended

power arrangements, with VA and VCP connected to clean supplies. VL, which powers the digital circuitry,
may be run from the system logic supply. Alternatively, VL may be powered from the analog supply via a
ferrite bead. In this case, no additional devices should be powered from VL.

7.2

Grounding

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors must be as close to the pins of the CS42L73 as pos-
sible. The low value ceramic capacitor must be closest to the pin and must be mounted on the same side
of the board as the CS42L73 to minimize inductance effects. All signals, especially clocks, must be kept
away from the FILT+, ANA_VQ, and SPK_VQ pins in order to avoid unwanted coupling into the modulators.
The FILT+, ANA_VQ, SPK_VQ, +VCP_FILT and -VCP_FILT capacitors must be positioned to minimize the
electrical path from each respective pin to AGND (PGND with respect to SPK_VQ).

7.3

Layout With Fine-Pitch, Ball-Grid Packages

PCB layouts with fine-pitch, ball-grid packages, such as those available for the CS42L73, can benefit from
using the particular layout approaches. This is especially true when routing to/from balls inside the outer ring
of the package’s ball array. Using the via-in-pad, filled-micro-via, and blind-via technologies can ease rout-
ing congestion, allowing access to all the packages balls. For more detailed layout assistance, please con-
tact Cirrus Logic.

7

6

5

4

3

2

1

0

FM15

FM14

FM13

FM12

FM11

FM10

FM9

FM8

7

6

5

4

3

2

1

0

FM7

FM6

FM5

FM4

FM3

FM2

FM1

FM0