2 power-up sequence (xsp to hp/lo), Cs42l73 – Cirrus Logic CS42L73 User Manual
Page 66
66
DS882F1
CS42L73
signal may be applied any time during the power-up sequence. If an MCLK signal is present when
RESET is brought high, it is recommended that the rising edge of RESET be synchronized to the
falling edge of MCLK. After RESET is brought high, the MCLK signal must not have any glitched
pulses. A glitched pulse is any pulse that is shorter than the period defined by the minimum/max-
imum MCLK signal duty cycle specification and the nominal frequency of the MCLK; see the spec-
ifications on
.
4.12.2 Power-Up Sequence (xSP to HP/LO)
This sequence powers up the CS42L73 and sets basic mixing paths to achieve a playback path to the
headphones or lineout. Other output path settings can be substituted for HP/LO. Execute this sequence
when playback is desired after either the initial power-up sequence or the power-down sequence.
1. Start with the sequence specified in
“Initial Power-Up Sequence” on page 65
. If power is already
applied, the CS42L73 is to be awakened from a powered down state (refer to section
Sequence (xSP to HP/LO)” on page 67
) using the following procedure. In either case, the device is in
a PDN, PDN_HP/PDN_LO, PDN_xSPSDIN = 1b condition at this point.
2. Activate the MCLK signal feeding one of the MCLKx pins. Configure the internal MCLK according to
which pin the clock is applied to. Refer to
Section 4.2 “Internal Master Clock Generation” on page 42
for the required configuration. Enable the internal MCLK signal by clearing MCLKDIS.
Register Controls: MCLKSEL, MCLKDIV, and MCLKDIS
3. To minimize pops on the headphone or line amplifier, the respective analog output must first be
muted. Apply the mute immediately by ensuring Analog Soft Ramping (ANLGOSFT) is disabled
before changing the HP/LO settings.
Register Controls: ANLGOSFT and then
Register Controls: HPxAMUTE/LOxAMUTE
4. Now that the headphone or line amplifiers are muted, start the power-up of the core and HP/LO DAC.
Register Controls: PDN and PDN_HP/PDN_LO
5. If the serial port (xSP) is to be operated in slave mode, activate the external xSP clock signals (xSP_
SCLK and xSP_LRCK).
6. Configure the serial port.
Register Controls: Refer to the xSP control and master mode clocking control registers.
7. Power up the xSP input path.
Register Controls: PDN_xSPSDIN
8. Configure digital volume/muting for the ramping desired for audio startup:
• Analog soft ramping. Set the associated enable bit now that the analog mutes have had time to be
applied.
Register Controls: ANLGOSFT, mixer volumes
• Digital soft ramping. Ensure the digital mixer and/or HP/LO DAC digital volume is muted and digital
soft-ramping is configured/enabled.
Register Controls: DIGSFT, HLxDMUTE, mixer volumes
• No soft ramping. Configure the digital and analog soft-ramp controls accordingly and set the digital
mixer volume to the desired level.
Register Controls: ANLGOSFT, DIGSFT, mixer volumes
9. Set analog volumes, according to whether soft ramping is used:
• Soft ramping (digital or analog). Set the desired analog volumes on the HP/LO output.
• No soft-ramping. Set the analog volume to maximum attenuation.
Register Controls: HPx_AVOL/LOx_AVOL
10. Set the desired digital volume on the HP/LO output.
Register Controls: HLx_DVOL
11. Wait for the headphone/line amplifier to finish powering up. For most configurations, the used ASRC
should lock during this time (refer to section
) as indicated by the status bit