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5 vsp sdin location, 6 vsp sclk source equals mclk, 15 vsp master mode clocking control (address 11h) – Cirrus Logic CS42L73 User Manual

Page 92: 1 vsp master/slave mode, 2 vsp master mode clock control dividers, P 92, Vsp master/slave mode, Cs42l73

5 vsp sdin location, 6 vsp sclk source equals mclk, 15 vsp master mode clocking control (address 11h) | 1 vsp master/slave mode, 2 vsp master mode clock control dividers, P 92, Vsp master/slave mode, Cs42l73 | Cirrus Logic CS42L73 User Manual | Page 92 / 139 5 vsp sdin location, 6 vsp sclk source equals mclk, 15 vsp master mode clocking control (address 11h) | 1 vsp master/slave mode, 2 vsp master mode clock control dividers, P 92, Vsp master/slave mode, Cs42l73 | Cirrus Logic CS42L73 User Manual | Page 92 / 139
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