Cirrus Logic CDB42L51 - Manual (Page 4)

4 DS679DB2
CDB42L51
1. SYSTEM OVERVIEW
The CDB42L51 evaluation board is an excellent means for evaluating the CS42L51 CODEC. Digital audio signal
interfaces are provided, and an FPGA is used for easily configuring the board.
Section 2. “Software Mode Control”
on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.
The CDB42L51 schematic set has been partitioned into six pages and is shown in Figures 18 through 23 . “System
Connections and Jumpers” on page 17 provides a description of all stake headers and connectors, including the
default factory settings for all jumpers.
1.1 Power
Power is supplied to the evaluation board through the +5.0 V binding posts. Jumpers connect the CODEC’s
supplies to a regulated voltage of +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or 2.5 V for VD, VA and VA_HP.
All voltage inputs must be referenced to the black binding post ground connector.
For current measurement purposes only, a series resistor is connected to each supply. The current is easily
calculated by measuring the voltage drop across this resistor. NOTE: The stake headers connected in par-
allel with these resistors must be shunted with the supplied jumper during normal operation.
WARNING: Please refer to the CS42L51 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS42L51 requires careful attention to power supply and grounding arrangements to optimize perfor-
mance. The CDB42L51 demonstrates these optimal arrangements.
Figure 17 on page 19 provides an over-
view of the connections to the CS42L51. Figure 24 on page 26 shows the component placement, Figure 25
on page 27 shows the top layout, and Figure 26 on page 28 shows the bottom layout. The decoupling ca-
pacitors are located as close to the CS42L51 as possible. Extensive use of ground plane fill in the evaluation
board yields large reductions in radiated noise.
1.3 FPGA
The FPGA provides digital signal routing between the CS42L51, CS8406, CS8415 and the I/O stake head-
er. It also configures the hardware mode options of the CS8406 and CS8415 and provides routing control
of the system master clock from an on-board oscillator, the CS8415 and the I/O stake header. The Cirrus
FlexGUI software and “FPGA H/W Control” switches provide full control of the FPGA’s routing and config-
uration options.
Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on
page 13 provide configuration details.
1.4 CS42L51 Audio CODEC
A complete description of the CS42L51 ( Figure 18 on page 20 ) is included in the CS42L51 product data
sheet.
The CS42L51 may be configured using either the Cirrus FlexGUI or the on-board “CS42L51 H/W Control”
switches. The Software Mode control port registers are accessible through the “Register Maps” tab of the
Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional
tabs provide high-level control. The Hardware Mode, stand-alone controls for the CS42L51 are accessible
through the on-board, stand-alone switches, “CS42L51 H/W Control.”
Clock and data source selections are made in the control port of the FPGA, accessible through the “General
Configurations” tab of the Cirrus FlexGUI software or through the on-board “FPGA H/W Control” switches.
Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide
configuration details. provide configuration details.