Cirrus Logic CDB42L51 - Manual (Page 2)

2 DS679DB2
CDB42L51
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................ 4
1.1 Power ............................................................................................................................................. 4
1.2 Grounding and Power Supply Decoupling ...................................................................................... 4
1.3 FPGA .............................................................................................................................................. 4
1.4 CS42L51 Audio CODEC ................................................................................................................ 4
1.5 CS8406 Digital Audio Transmitter .................................................................................................. 5
1.6 CS8415 Digital Audio Receiver ...................................................................................................... 5
1.7 Oscillator ......................................................................................................................................... 5
1.8 I/O Stake Headers .......................................................................................................................... 5
1.9 Analog Input ................................................................................................................................... 6
1.10 Analog Outputs ............................................................................................................................. 6
1.11 Stand-Alone Switches .................................................................................................................. 6
1.12 USB and RS-232 Control Port Connectors .................................................................................. 6
2. SOFTWARE MODE CONTROL ............................................................................................................ 7
2.1 General Configuration Tab ............................................................................................................. 8
2.2 CODEC Configuration Tab ............................................................................................................. 9
2.3 ADC Volume Controls Tab ........................................................................................................... 10
2.4 DAC Volume Controls Tab ........................................................................................................... 11
2.5 Register Maps Tab ....................................................................................................................... 12
3. HARDWARE MODE CONTROL ......................................................................................................... 13
3.1 FPGA H/W Control ....................................................................................................................... 13
3.2 CS42L51 H/W Control .................................................................................................................. 17
4. SYSTEM CONNECTIONS AND JUMPERS ....................................................................................... 17
5. CDB42L51 BLOCK DIAGRAM ........................................................................................................... 19
6. CDB42L51 SCHEMATICS .................................................................................................................. 20
7. CDB42L51 LAYOUT ........................................................................................................................... 26
8. ERRATA .............................................................................................................................................. 29
9. REVISION HISTORY ........................................................................................................................... 29
LIST OF FIGURES
Figure 1. General Configuration Tab........................................................................................................... 8
Figure 2. CODEC Configuration Tab .......................................................................................................... 9
Figure 3. ADC Volume Controls Tab......................................................................................................... 10
Figure 4. DAC Volume Controls Tab......................................................................................................... 11
Figure 5. Register Maps Tab - CS42L51 .................................................................................................. 12
Figure 6. Routing 0.................................................................................................................................... 14
Figure 7. Routing 1.................................................................................................................................... 14
Figure 8. Routing 3.................................................................................................................................... 14
Figure 9. Routing 4.................................................................................................................................... 15
Figure 10. Routing 5.................................................................................................................................. 15
Figure 11. Routing 6.................................................................................................................................. 15
Figure 12. Routing 7.................................................................................................................................. 15
Figure 13. Routing 8.................................................................................................................................. 16
Figure 14. Routing 9.................................................................................................................................. 16
Figure 15. Routing 10................................................................................................................................ 16
Figure 16. Routing 11................................................................................................................................ 16
Figure 17. Block Diagram.......................................................................................................................... 19
Figure 18. CS42L51 and Analog I/O (Schematic Sheet 1) ....................................................................... 20
Figure 19. S/PDIF I/O (Schematic Sheet 2) .............................................................................................. 21
Figure 20. FPGA (Schematic Sheet 3)...................................................................................................... 22
Figure 21. Level Shifters & I/O Stake Header (Schematic Sheet 4) ......................................................... 23
Figure 22. Control Port I/O (Schematic Sheet 5) ...................................................................................... 24