beautypg.com

Single-rank and dual-rank dimms, Memory subsystem architecture, Ecc memory – HP ProLiant DL320e Gen8 v2-Server User Manual

Page 46

background image

Hardware options installation 46

Item Description

Definition

x8 = 8-bit

4

Voltage rating

L = Low voltage (1.35v)

U = Ultra low voltage (1.25v)
Blank or omitted = Standard

5

Memory speed

12800 = 1600-MT/s

10600 = 1333-MT/s
8500 = 1066-MT/s

6

DIMM type

R = RDIMM (registered)

E = UDIMM (unbuffered with ECC)

L = LRDIMM (load reduced)
H = HDIMM (HyperCloud)

For the latest supported memory information, see the QuickSpecs on the HP website
(

http://h18000.www1.hp.com/products/quickspecs/ProductBulletin.html

). At the website, choose the

geographic region, and then locate the product by name or product category.

Single-rank and dual-rank DIMMs

DIMM configuration requirements are based on these classifications:

Single-rank DIMM—One set of memory chips that is accessed while writing to or reading from the
memory.

Dual-rank DIMM—Two single-rank DIMMs on the same module, with only one rank accessible at a time.

The server memory control subsystem selects the proper rank within the DIMM when writing to or reading

from the DIMM.
Dual-rank DIMMs provide the greatest capacity with the existing memory technology. For example, if current

DRAM technology supports 2-GB single-rank DIMMs, a dual-rank DIMM would be 4 GB.

Memory subsystem architecture

The memory subsystem in this server is divided into channels. The processor supports two channels, and each

channel supports two DIMM slots.

Channel

Population order

Slot number

1

C

A

4

3

2

D

B

2

1

DIMM slots are identified by number and by letter. Letters identify the population order. Slot numbers are

reported by ROM messages during boot and are used for error reporting. For the DIMM slot locations, see

"DIMM slot locations (on page

10

)."

ECC memory

The server supports the standard ECC memory correction mode. Standard ECC can correct single-bit memory

errors and detect multibit memory errors. When multibit errors are detected, the error is signaled to the server

and causes the server to halt.