PNI SENtral MandM - Manual (Page 12)

PNI Sensor Corporation Doc #1020129 revE
SENtral M&M Technical Datasheet Page 11
either by the host or SENtral. Normally the serial clock line will be driven by the host,
although exceptions can exist when clock-stretching is implemented in Pass-Through State.
3.2.1 I
2
C Transfer formats
Figure 3-2 illustrates writing data to registers in single-byte or multiple-byte mode.
START SLAVE ADDRESS RW ACK REGISTER ADDRESS (N) ACK DATA TO REGISTER (N) ACK DATA TO REGISTER (N+1) ACK STOP
S A6 A5 A4 A3 A2 A1 A0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 P
From Host to SENtral
------------ Data Transferred (n bytes + acknowledge) ------------
From SENtral to Host
Figure 3-2: I
2
C Slave Write Example
The I
2
C host interface supports both a read sequence using repeated START conditions,
shown in Figure 3-3, and a sequence in which the register address is sent in a separate
sequence than the data, shown in Figure 3-4 and Figure 3-5.
START SLAVE ADDRESS RW ACK REGISTER ADDRESS (N) ACK START SLAVE ADDRESS RW ACK DATA FROM REGISTER (N) NACK STOP
S A6 A5 A4 A3 A2 A1 A0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 0 SR A6 A5 A4 A3 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 P
Data Transferred
(n bytes + acknowledge)
Figure 3-3: I 2 C Slave Read Example, with Repeated START
START SLAVE ADDRESS RW ACK REGISTER ADDRESS (N) ACK STOP
S A6 A5 A4 A3 A2 A1 A0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 0 P
Figure 3-4: I 2 C Slave Write Register Address Only
START SLAVE ADDRESS RW ACK DATA FROM REG. (N) ACK DATA FROM REG. (N+1) NACK STOP
S A6 A5 A4 A3 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 P
From Host to SENtral
-------------- Data Transferred (n bytes + acknowledge) --------------
From SENtral to Host
Figure 3-5: I 2 C Slave read register from current address