AMD SEMPRON 10 - Manual (Page 15)

Chapter 1 Overview 3
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
1.1 QuantiSpeed™ Architecture Summary
The following design features summarize the QuantiSpeed
architecture of the AMD Sempron processor model 10 with
256K of L2 cache:
■ A nine-issue, superpipelined, superscalar x86 processor
microarchitecture designed for increased instructions per
cycle (IPC) and high clock frequencies
■ Pipelined floating-point unit that executes all x87
(floating-point), MMX
, SSE and 3DNow! instructions
■ Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing
high-bandwidth system capabilities
■ Advanced two-level translation look-aside buffer (TLB)
structures for both enhanced data and instruction address
translation. The AMD Sempron processor model 10 with
QuantiSpeed architecture incorporates three TLB
optimizations: the L1 DTLB increases from 32 to 40 entries,
the L2 ITLB and L2 DTLB both use exclusive architecture,
and the TLB entries can be speculatively loaded.
The AMD Sempron processor model 10 delivers excellent
system performance in a cost-effective, industry-standard form
factor. The AMD Sempron processor model 10 is compatible
with motherboards based on Socket A.
Figure 1 on page 4 shows a typical AMD Sempron processor
model 10 with 256K L2 cache system block diagram.