Teledyne LeCroy QPHY-DDR2 - Manual (Page 8)

8
QPHY-DDR2-OM-E Rev A
Burst Read
The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the
rising edge of the clock. The address inputs determine the starting column address for the burst. The data strobe
output (DQS) is driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the
burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ
pin in phase with the DQS signal in a source synchronous manner.
Figure 1. Data output (read) timing [JESD79-2E figure 32]
Figure 2. Burst read followed by burst write [JESD79-2E figure 35]
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-
around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.