QPHY-DDR2 Software Option
QPHY-DDR2-OM-E Rev
A
5
tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 35
tJIT(duty), Half Period Jitter ....................................................................................................................................... 35
tJIT(per), Clock Period Jitter ...................................................................................................................................... 36
tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 36
tERR(n per), Cumulative Error ................................................................................................................................... 36
Eye Diagram ............................................................................................................................................................ 37
Write Burst (Inputs) .................................................................................................................................................... 37
Read Burst (Outputs) ................................................................................................................................................. 37
Electrical Tests ......................................................................................................................................................... 37
Write Bursts (Inputs) ......................................................................................................................................... 37
Slew (Input Slewrate) ..................................................................................................................................................... 37
SlewR and SlewF ....................................................................................................................................................... 37
Logic Levels ................................................................................................................................................................... 37
VIH(ac), maximum AC input logic high ....................................................................................................................... 37
VIH(dc), minimum DC input logic high ....................................................................................................................... 38
VIL(ac), maximum AC input logic low ......................................................................................................................... 38
VIL(dc), minimum DC input logic low ......................................................................................................................... 38
VSWING(MAX), input signal maximum peak to peak swing ...................................................................................... 38
AC Over/Undershoot ...................................................................................................................................................... 38
AC Overshoot, Maximum peak amplitude .................................................................................................................. 38
AC Overshoot, Maximum overshoot area above VDDQ ............................................................................................ 38
AC Undershoot, Maximum peak amplitude ................................................................................................................ 38
AC Undershoot, Maximum overshoot area above VDDQ .......................................................................................... 39
Tests Requiring Single Ended Probing of Differential Signal ......................................................................................... 39
VID(ac), AC Differential Input Voltage ........................................................................................................................ 39
VIX(ac), AC Differential Input Cross Point Voltage..................................................................................................... 39
Read Bursts (Outputs) ...................................................................................................................................... 39
Sout (Output Slew Rate) ................................................................................................................................................ 39
SoutR and SoutF ........................................................................................................................................................ 39
tSLMR ........................................................................................................................................................................ 39
Tests Requiring Single Ended Probing of Differential Signal ......................................................................................... 40
VOX(ac) , AC Differential Output Cross Point Voltage ............................................................................................... 40
Timing Tests ............................................................................................................................................................. 40
Read Bursts ...................................................................................................................................................... 40
tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals ....................................................................................... 40
tHP, CK half pulse width ................................................................................................................................................ 41
tQHS, DQ hold skew factor ............................................................................................................................................ 41
tQH, DQ/DQS Output Hold Time From DQS.................................................................................................................. 41
tDQSCK, DQS Output Access Time from CK/CK # ....................................................................................................... 41
tAC, DQ Output Access Time from CK/CK# .................................................................................................................. 41
tHZ(DQ), DQ High Impedance Time From CK/CK# ....................................................................................................... 42
tLZ(DQ), DQ Low-Impedance Time from CK/CK# ......................................................................................................... 42
tLZ(DQS), DQS Low-Impedance Time from CK/CK# ..................................................................................................... 42
tRPRE, Read Preamble ................................................................................................................................................. 42
tRPST, Read Postamble ................................................................................................................................................ 42
Write Bursts ...................................................................................................................................................... 43
tDQSS, DQS latching rising transitions to associated CK edge ..................................................................................... 43
tDQSH, DQS Input High Pulse Width ............................................................................................................................. 43
tDQSL, DQS Input Low Pulse Width .............................................................................................................................. 43
tDSS, DQS Falling Edge to CK Setup Time ................................................................................................................... 43
tDSH, DQS Falling Edge Hold Time from CK ................................................................................................................ 43
tWPRE, Write Preamble ................................................................................................................................................. 44
tWPST, Write Postamble ............................................................................................................................................... 44
tDS(base), DQ and DM Input Setup Time ...................................................................................................................... 44
tDH(base), DQ and DM Input Hold Time ........................................................................................................................ 44
tDS1(base), DQ and DM input setup time (single-ended strobe) ................................................................................... 45
tDH1(base), DQ and DM input hold time (single-ended strobe) ..................................................................................... 45
tIS(base) - Address and Control Input Setup Time ......................................................................................................... 46
tIH(base) - Address and Control Input Hold Time .......................................................................................................... 47
