Teledyne LeCroy QPHY-DDR2 - Manual (Page 32)

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QPHY-DDR2-OM-E Rev A
Silent mode control
No more interaction with the user when silent mode is on. Choose between Yes or No. Default is No. This is
useful to let the test run without interruption in the background.
Stop On Test to review results
When set to Yes, the script stops after each test allowing you to view the results. The setup is saved so the
oscilloscope settings can be modified by the user. On resume, the setup is recalled. Any new acquisition done
may cause the script to produce unexpected results.
Waveform Path
Specify the path on the oscilloscope to save/recall waveforms. When not in Demo Mode and when Save
acquired waveforms is enabled, the waveforms are saved in this folder. When set to Demo Mode or when Use
stored trace for pixel clock measure, waveforms are also available from this folder. The default location is
D:\Waveforms\DDR2.
Demo Settings
Use Stored Waveforms
When enabled, previously stored DDR2 waveforms is used. Default is No.
Recalled Waveform File Index (5 digits)
Enter the 5 digits number corresponding to the index of the file you want to recall. Default is 00000.
Define format used to set trace names
Stores a saved waveform naming format or convention The choices are LeCroy or Dialog. The LeCroy choice
produces waveform names automatically by the software. Dialog prompts the user for custom waveform names.
The default setting is LeCroy.
Use Stored Trace for Speed Grade
This is an optimization used specifically to measure the clock frequency only once. Choose from Yes or No
values, The default selection is No.
Advanced Settings
Clock Period per Screen Division
Oscilloscope timebase and sampling rate is set to acquire the given number of clock cycle per display horizontal
division at a given DUT Speed Grad in MT/s and for a Max. Number of Samples Per Clock Period. The default
is 3341 clock periods (this gives a 10us/div timebase at 667 MT/s and 3.3MS max for 100 samples per period).
Timebase = [Clock Period Per Screen Division] / ([DUT Speed Grade in MT/s] / 2 * 1e6)
Maximum Samples = [Max. Number Of Samples Per Clock Period] * [Clock Period Per Screen Division] * 10
Number of cycles for Clock test
Jedec standard requires 200 cycles for the Clock compliance test.
This is the default value of this variable. Any positive number can be entered.
Max. Number Of Samples Per Clock Period
The oscilloscope timebase and sampling rate is set to acquire the given number of points per clock period. The
oscilloscope is always set to at least acquire at 20GS/s. Additionally, if an oscilloscope with greater than 6GHz
bandwidth is used, the bandwidth is limited to 6GHz. See the Clock Period Per Screen Division topic for more
details. Choose between 10;20;50;100;200;500 or 1000. The default value is 100.