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4 chipset, Dram ras# to cas# delay [3, Dram ras# precharge [3 – Asus AP1720-E2 User Manual

Page 124: System bios cacheable [enabled, Video bios cacheable [disabled, Chapter 5: bios setup 5-20

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Chapter 5: BIOS setup

5-20

DRAM RAS# to CAS# Delay [3]

Controls the latency between the DRAM active command and the read/
write command. Configuration options: [4] [3] [2]

DRAM RAS# Precharge [3]

This item controls the idle clocks after issuing a precharge command to
the DDR SDRAM. Configuration options: [4] [3] [2]

Memory Parity Check [Enabled]

Allows memory parity checking option ECC (Error-Correcting Code).
Configuration options: [Disabled] [Enabled]

5.4.4 Chipset

This menu shows the chipset configuration settings. Select an item then
press to display a sub-menu with additional items, or show a
pop-up menu with the configuration options.

System BIOS Cacheable [Enabled]

Allows you to enable or disable the cache function of the system BIOS.
Configuration options: [Disabled] [Enabled]

Video BIOS Cacheable [Disabled]

Allows you to enable or disable the cache function of the video BIOS.
Setting to [Enabled] improves the display speed by caching the display
data. Configuration options: [Disabled] [Enabled]

AGP Bridge Configuration
Frequency/Voltage Control
System BIOS Cacheable

[Enabled]

Video BIOS Cacheable

[Disabled]

Init Display First

[AGP Slot]

Auto Detect PCI Clk

[Enabled]

Spread Spectrum

[+/- 0.50%]

Chipset

Item Specific Help

Press to set.

Select Menu