Atec Rohde-Schwarz-SMJ100A - Manual (Page 19)

Version 05.00, December 2007 R&S ® SMJ100A Vector Signal Generator 19
In internal clock mode, a trigger event
restarts the clock generation. The clock
phase is then synchronous with the trigger
(with a certain timing uncertainty).
In external clock mode, the trigger event is
synchronized to the symbol clock.
operating mode internal, external
modes Auto, Retrig, Armed Auto, Armed Retrig
setting uncertainty for clock phase related
to trigger in internal clock mode <18 ns
external trigger delay
setting range 0 sample to (2 16 – 1) sample
resolution
internal clock mode 0.01 sample
external clock mode 1 sample
setting uncertainty <5 ns
external trigger inhibit
setting range 0 sample to (2 26 – 1) sample
resolution 1 sample
external trigger pulse width >15 ns
Triggering
external trigger frequency <0.02 × sampling rate
number 4
level LVTTL
operating modes
unchanged, restart, pulse, pattern, ratio
marker delay
setting range 0 sample to (waveform length − 1) sample
setting range without recalculation 0 sample to 2000 sample
resolution of setting 0.001 sample
Marker outputs
setting uncertainty <10 ns
Operation with R&S ® WinIQSIM2™: As of version 2.04, the software supports I/Q data download and control of the
R&S ® SMJ-B9/-B10/-B11/-B50/-B51.
Operation with R&S ® WinIQSIM™: As of version 4.50, the software supports I/Q data download and control of the
R&S ® SMJ-B9/-B10/-B11/-B50/-B51.