Atec Agilent-34980A - Manual (Page 16)

34950A 64-channel digital
I/O with memory and counter
This module can be used to simulate
or detect digital patterns. It has eight
8-bit digital I/O channels with hand-
shaking, pattern memory, two 10-MHz
totalizers with gate functions, and a
programmable clock output.
Digital input/output
The digital I/O bits are organized into
two banks of 32-bits. The I/O bits can
be configured and programmed as
inputs or outputs in 8-bit channels.
The digital outputs can be configured
as active drive or tristate outputs
with user supplied pull up resistors
for up to 5 V outputs. The digital
inputs have programmable thresholds
up to 5 V for compatibility with most
digital logic standards.
The onboard pattern memory can
be used to select and output digital
stimulus or bitstream patterns, or to
capture external digital data. Each
bank has independent memory and
directional control so that one bank
can output data while the other
captures data. The memory can
be divided into 16 Kbytes per 8-bit
channel, or you can specify all the
memory onto a single channel on the
bank, resulting in 64 Kbytes on each
bank.
Specifically, the digital I/O channels
also have:
• Variable active high drive output
from 1.5 V to 5 V or tristate
• Variable input thresholds from
1.5 V to 5 V
• 7 configurable handshaking
protocols including synchronous,
asynchronous, and strobe
• Programmable polarity
• Source or sink up to 30 mA
• Internal alarming for maskable
pattern match
• 1 hardware interrupt per bank
• Connections via standard 78-pin
Dsub cables or detachable terminal
block
Frequency counter/totalizer
The two channels can be used to
count events, frequency, period, duty
cycle, totalize, and pulse width. The
counter/totalizer also includes
• Programmable gate functionality
• Programmable input thresholds
levels 1.5 V to 5 V
Digital input/output characteristics –
preliminary specs, contact factory
Eight 8-bit channels:
8 bits wide, input or output, non-isolated
Vin 1.5 V – 5 V
(1)
Vout 1.5 V – 5V
(1)
Iout (max) 30 mA
(2)
Frequency (max) 10 MHz [3]
Handshake lines
Vin 1.5 – 5 V
(1)
Vout 1.5 – 5 V
(1)
Low Voltage Range 0 – 5 V
Frequency (max) 10 MHz
(1) Configurable by 8-bit channel
(2) Current limit per bit
(3) from memory with handshaking
Counter function characteristics
Maximum freq 10 MHz (max) 50% duty
cycle
Vin 1.5 V – 5 V
Totalizer function characteristics
Maximum count 2^32 – 1 (4,294,967,296)
Max input freq 10 MHz (max),
rising or falling edge
programmable
Vin 1.5 V – 5 V
Gate input 1.5 V – 5 V
System clock generator characteristics
Frequency 10 MHz – 10 Hz configurable
divide-by-n 24-bits,
programmable on/off
Vout 1.5 V – 5 V
Accuracy: 100 ppm
16
DIO
bank
1
Counter/
totalizer
1
Channel
01
8
32 Bits
8
8
8
Bit0
Bit7
Interupt
Channel
09
Channel
02
Bit8
Bit15
Channel
03
Bit16
Bit23
Channel
04
Bit24
Bit31
Flag
Ctl
I/O
IN
Gate
IN
Gate
Counter/
totalizer
2
32 Bits Channel
10
Clock
out
24 Bits
20 MHz – 10 Hz
Channel
11
DIO
bank
2
Channel
05
8
8
8
8
Bit32
Bit39
Interupt
Channel
06
Bit40
Bit47
Channel
07
Bit48
Bit55
Channel
08
Bit56
Bit63
Flag
Ctl
I/O
34980A system control modules
Figure 10. 34950A 64-channel digital I/O