Rainbow Electronics AT45DB321D - Manual (Page 4)

4
3597J–DFLASH–4/08
AT45DB321D
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
FLASH MEMORY ARRAY
PAGE (512/528 BYTES)
BUFFER 2 (512/528 BYTES) BUFFER 1 (512/528 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SO SI
SECTOR 0a = 8 Pages
4,096/4,224 bytes
SECTOR 0b = 120 Pages
61,440/63,360 bytes
Block = 4,096/4,224 bytes
8 Pages SECTOR 0a
S
ECT
OR 0b
Page = 512/528 bytes
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 8,190
PAGE 8,191
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1,022
BLOCK 1,023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
S
ECT
OR 1
SECTOR 63 = 128 Pages
65,536/67,586 bytes
BLOCK 2
SECTOR 1 = 128 Pages
65,536/67,584 bytes
SECTOR 62 = 128 Pages
65,536/67,584 bytes
SECTOR 2 = 128 Pages
65,536/67,584 bytes