Rainbow Electronics AT49F8192AT - Manual (Page 5)

5
AT49F008A(T)/8192A(T)
1199F–04/01
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the
Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identification Entry/Exit” on page 12. The
manufacturer and device codes are the same for both modes.
DATA POLLING: The AT49F008A(T)/8192A(T) features Data Polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector
erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true
data will be read from the device. Data Polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49F008A(T)/8192A(T) provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
READY/BUSY: For the AT49F008A(T), pin 12 is an open-drain Ready/Busy output pin, which provides another method of
detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase
cycles and it is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to
the same RDY/BUSY line.
H A R D W A R E D A T A P R O T E C T I O N : H a r d w a r e f e a t u r e s p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49F008A(T)/8192A(T) in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V (typical), the program function is inhib-
ited. (b) V
CC
power-on delay: once V
CC
has reached the V
CC
sense level, the device will automatically time-out 10 ms (typi-
cal) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.