Rainbow Electronics AT45DB011D - Manual (Page 50)

50
3639J–DFLASH–11/2012
AT45DB011D
28. Revision History
Revision Level – Release Date History
A – June 2006 Initial Release
B – February 2007 Removed RDY/BUSY pin references.
C – November 2007
Fixed the typographical error in the Block Architecture diagram.
Changed t
VCSL
time to 1ms.
Changed I
DP
(Max) to 15µA.
Added Chip Erase time.
Changed t
RDPD
time to 35µs.
Changed the t
XFR
and t
COMP
times from 400µs to 200µs.
Changed part number ordering code to reflect NiPdAu lead finish.
- Changed AT45DB011D-SSU to AT45DB011D-SSH.
- Changed AT45DB011D-SU to AT45DB011D-SH.
- Changed AT45DB011D-MU to AT45DB011D-MH.
Added lead finish details to Ordering Information table.
Added Ordering Code Detail.
D – March 2008
Changed I
CC1
(Typ) and I
CC1
(Max), for f = 66MHz, to 15mA and
25mA, respectively.
Changed I
CC2
(Max) to 20mA.
Changed t
BE
(Typ) to 18ms.
Changed 8M1-A MLF package to 8MA1 UDFN package.
E – May 2008 Added part number ordering code details for suffixes SL954/955.
F – February 2009 Changed t
DIS
(Typ and Max) to 27ns and 35ns, respectively.
G – March 2009
Changed Deep Power-Down Current values
- Increased typical value from 5µA to 15µA.
- Increased maximum value from 15µA to 25µA.
H – April 2009 Updated Absolute Maximum Ratings
I – May 2010
Changed t
SE
(Typ) 0.8 to 0.4 and (Max) 2.5 to 0.7.
Changed t
CE
(Typ) 1.8 to 1.2.
Changed from 10,000 to 20,000 cumulative page erase/program
operations in section 11.3.
Added “Please contact Adesto for availability of devices that are
specified to exceed the 20K cycle cumulative limit” in section 11.3
.
J – November 2012 Update to Adesto logos.