Max6900, C-compatible rtc in a tdfn, Chip information – Rainbow Electronics MAX6900 User Manual
Page 14
MAX6900
14
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determine frequency stability, use the parabolic curve
in Figure 10 and the following equations:
∆f = f
✕
k
✕
(T
0
- T )
2
where:
∆
f
= change in frequency from +20°C.
f = nominal crystal frequency.
k = parabolic curvature constant (-0.035
±0.005ppm/°C
2
for 32.768kHz watch crystals).
T
0
= turnover temperature
(+25°C ±5°C for 32.768kHz watch crystals).
T = temperature of interest (°C).
For example: What is the worst-case change in oscilla-
tor frequency from +25°C to +45°C ambient?
∆
f
(worst case) = 32,768
✕
(-0.04 / 1
✕
10e6)
✕
(20 -45)
2
= -0.8192Hz
After 1 month, that translates to:
Assuming ±20ppm initial crystal tolerance (±53s initial
accuracy); total worst-case timekeeping error at the
end of 1 month = 66.96s - 53s = -119.96s or about 2
minutes (assumes negligible parasitic layout capaci-
tance).
Power-Supply Considerations
For most applications, a 0.1µF capacitor from V
CC
to
GND provides adequate bypassing for the MAX6900.
Because the MAX6900’s supply current is well under
1µA, a series resistor can be added to the supply to
reject extremely harsh noise.
PC Board Layout Considerations
When designing the PC board, keep the crystal as
close to the X1 and X2 pins of the MAX6900 as possi-
ble (Figure 11). Keep the trace lengths short and small
to avoid introducing excessive capacitive loading and
preventing unwanted noise pickup. Place a guard ring
around the crystal and tie the ring to ground to help iso-
late the crystal from unwanted noise pickup. Keep all
signals away from the crystal and the X1 and X2 pins to
prevent noise coupling. Finally, an additional local
ground plane on an adjacent PC board layer can be
added under the crystal to shield it from unwanted
pickup from traces on other layers of the board. This
plane should be isolated from the regular PC board
ground plane and tied to the GND pin of the MAX6900.
This plane needs to be no larger than the perimeter of
the guard ring. Ensure that this ground plane does not
contribute to significant capacitance between ground
and the traces that run from X1 and X2 to the crystal.
Chip Information
TRANSISTOR COUNT: 19,307
PROCESS: CMOS
∆
t
31days
24
hr
day
60
min
hr
60
s
min
-0.8192Hz
32768Hz
66.96s
=
(
)
Ч
Ч
Ч
Ч
=
TYPICAL TEMPERATURE CHARACTERISITICS
(k = -0.035ppm/
°C
2
, T
O
= +25
°C)
∆
f (ppm)
TEMPERATURE (
°C)
-250
-200
-150
-100
-50
0
-50 -40 -30 -20 -10
0
10
20
25
30
40
50
60
70
80
90
Figure 10. Typical Temperature Curve for 32.768kHz Watch Crystal
I
2
C-Compatible RTC in a TDFN