Rainbow Electronics U3741BM - Manual (Page 11)

11
U3741BM
4662B–RKE–10/04
• USA Applications
(f
XTO
= 4.90625 MHz, MODE = L, T
Clk
= 2.0383 µs)
• Europe Applications
(f
XTO
= 6.76438 MHz, MODE = H, T
Clk
= 2.0697 µs)
• Other applications
(T
Clk
is dependent on f
XTO
and on the logical state of pin MODE. The electrical
characteristic is given as a function of T
Clk
).
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T
XClk
is defined
by the following formulas for further reference:
Polling Mode According to Figure 3 on page 6, the receiver stays in polling mode in a continuous
cycle of three different modes. In sleep mode, the signal processing circuitry is disabled
for the time period T
Sleep
while consuming a low current of I
S
= I
Soff
. During the start-up
period, T
Startup
, all signal processing circuits are enabled and settled. In the following bit
check mode, the incoming data stream is analyzed bit by bit against a valid transmitter
signal. If no valid signal is present, the receiver is set back to sleep mode after the
period T
Bitcheck
. This period varies check by check as it is a statistical process. An aver-
age value for T
Bitcheck
is given in “Electrical Characteristics” on page 23. During T
Startup
and T
Bitcheck
the current consumption is I
S
= I
Son
. The average current consumption in
polling mode is dependent on the duty cycle of the active mode and can be calculated
as:
During T
Sleep
and T
Startup
, the receiver is not sensitive to a transmitter signal. To guaran-
tee the reception of a transmitted command, the transmitter must start the telegram with
an adequate preburst. The required length of the preburst is dependent on the polling
parameters T
Sleep
, T
Startup
, T
Bitcheck
and the startup time of a connected microcontroller
(T
Start,µC
). T
Bitcheck
thus depends on the actual bit rate and the number of bits (N
Bitcheck
) to
be tested.
The following formula indicates how to calculate the preburst length.
T
Preburst
≥
T
Sleep
+ T
Startup
+ T
Bitcheck
+ T
Start_ µ C
Sleep Mode The length of period T
Sleep
is defined by the 5-bit word Sleep of the OPMODE register,
the extension factor X
Sleep
, according to Figure 10 on page 13, and the basic clock cycle
T
Clk
. It is calculated to be:
In US and European applications, the maximum value of T
Sleep
is about 60 ms if X
Sleep
is
set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended
to almost half a second by setting X
Sleep
to 8. X
Sleep
can be set to 8 by bit X
SleepStd
or by
bit X
SleepTemp
resulting in a different mode of action as described below:
BR_Range = BR_Range0: T
XClk
= 8
×
T
Clk
BR_Range1: T
XClk
= 4
×
T
Clk
BR_Range2: T
XClk
= 2
×
T
Clk
BR_Range3: T
XClk
= 1
×
T
Clk
I
Spoll
I
Soff
T
Sleep
I
Son
T
Startup
T
Bitcheck
+
( ) Ч
+
Ч
T
Sleep
T
Startup
T
Bitcheck
+ +
------------------------------------------------------------------------------------------------------------ =
T
Sleep
Sleep X
Sleep
Ч
1024
Ч
T
Clk
Ч
=