Pin description – Rainbow Electronics MAX98089 User Manual
Page 57
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MAX98089
Low-Power, Stereo Audio Codec
with FlexSound Technology
Pin Description
BUMP
(WLP)
PIN
(TQFN-EP)
NAME
FUNCTION
A1, B1
15
SPKRN
Negative Right-Channel Class D Speaker Output
A2, B2
16
SPKRGND
Right-Speaker Ground
A3, B3
19
SPKLVDD
Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF
and a 10FF capacitor.
A4, B4
20
SPKLP
Positive Left-Channel Class D Speaker Output
A5, B5
22
SPKLN
Negative Left-Channel Class D Speaker Output
A6
24
RECP/LOUTL/
RXINP
Positive Receiver Amplifier Output or Left Line Output. Can be positive bypass
switch input when receiver amp is shut down.
A7
25
PVDD
Headphone Power Supply. Bypass to HPGND with a 1FF and a 10FF capacitor.
A8
31
HPVSS
Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
A9
30
HPGND
Headphone Ground
B6
23
RECN/LOUTR/
RXINN
Negative Receiver Amplifier Output or Right Line Output. Can be negative bypass
switch input when receiver amp is shut down.
B7
26
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic
capacitor between C1N and C1P.
B8
27
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic
capacitor between C1N and C1P.
B9
32
HPVDD
Noninverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capaci-
tor.
C1, C2
17
SPKRP
Positive Right-Channel Class D Speaker Output
C3, D3
18
SPKRVDD
Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
C4, C5
21
SPKLGND
Left-Speaker Ground
C6, C7, D5,
D6, D7, E3
11–14,
28, 29, 46
N.C.
No Connection
C8
34
HPSNS
Headphone Amplifier Ground Sense. Connect to the headphone jack ground
terminal for optimal performance or connect to PCB ground.
C9
33
HPL
Left-Channel Headphone Output
D1
8
BCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the IC is in slave
mode and an output when in master mode. The input/output voltage is referenced
to DVDDS1.
D2
7
SDOUTS1
S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to
DVDDS1.
D4
10
LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate
clock and determines whether S1 audio data is routed to the left or right channel.
In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the IC
is in slave mode and an output when in master mode.
D8
36
INB2
Single-Ended Line Input B2. Also positive differential line input B.
D9
35
HPR
Right-Channel Headphone Output