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Adv ance informa t ion – Texas Instruments TMS320 User Manual

Page 51

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TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

HOUSTON, TEXAS 77001

51

HOLD timing (part B)

CLKOUT1

CLKOUT2

STRB

HOLD

A15-A0

PS, DS,

or IS

R/W

D15-D0

HOLDA

FETCH

EXECUTE

t

d(C2H-H)

In

In

N + 2

N + 3

Valid

Valid

N/A

N /A

N + 2

N + 3

Dead

Dead

N + 1

N + 2

t

en(A-C1L)

t

d(HH-AH)

HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;
otherwise, a delay of one CLKOUT2 cycle will occur.

ADV

ANCE

INFORMA

T

ION