Texas Instruments TMS320 - Manual (Page 3)

TMS320 SECOND GENERATION
DIGITAL SIGNAL PROCESSORS
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001 3
description
The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed
controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to
multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and
flexibility to produce a MOS microprocessor family that is capable of executing more than 12.5 MIPS (million
instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other
processors implement through microcode or software. This hardware-intensive approach provides the design
engineer with processing power previously unavailable on a single chip.
The TMS320 family consists of three generations of digital signal processors. The first generation contains the
TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25,
which are described in this data sheet. The TMS320C30 is a floating-point DSP device designed for even higher
performance. Many features are common among the TMS320 processors. Specific features are added in each
processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the
family to protect the user’s investment in architecture. Each processor has software and hardware tools to
facilitate rapid design.
introduction
The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its
powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative
architecture have made this high-performance, cost-effective processor the ideal solution to many
telecommunications, computer, commercial, industrial, and military applications. Since that time, the
TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have
been added to the first generation of the TMS320 family.
The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the
TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon
that of the TMS32010.
The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many
applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set
(109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and
hardware timer make the TMS32020 a powerful addition to the TMS320 family.
The TMS320C25 is the second member of the TMS320 second generation. It is processed in CMOS technology,
is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object-code compatible with the
TMS32020. The TMS320C25’s enhanced feature set greatly increases the functionality of the device over the
TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an
eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and
the low-power dissipation inherent to the CMOS process. An extended-temperature range version
(TMS320C25GBA) is also available.
The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less
than 80 ns. It is architecturally identical to the original 40-MHz version of the TMS320C25 and, thus, is pin-for-pin
and object-code compatible with the TMS320C25.
The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is
replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and
modification for immediate evaluation of system performance.