IBM POWERPC 750GL - Manual (Page 183)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_05.fm.(1.2)
March 27, 2006 Memory Management
Page 183 of 377
Figure 5-1. MMU Conceptual Block Diagram
Optional
Instruction
Accesses
Data
Accesses
EA[0–19]
Segment Registers
•
•
•
On-Chip
TLBs
(Optional)
Page Table
Search Logic
(Optional)
SDR1 SPR 25
PA[0–14]
X
PA[0–19]
PA[15–19]
PA[0–31]
A[20–31]
IBAT0U
IBAT0L
IBAT7U
IBAT7L
•
•
DBAT0U
DBAT0L
DBAT7U
DBAT7L
•
•
EA[0–14]
EA[15–19]
EA[0–14]
EA[15–19]
A[20–31]
BAT
Hit
Upper 24-Bits
of Virtual Address
0
15
MMU
(32-Bit)
EA[0–3]
EA[4–19]
EA[0–19]
X
X
X