IBM POWERPC 750GL User Manual
Page 373
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umIX.fm.(1.2)
March 27, 2006
Index
Page 373 of 377
O
OEA
exception mechanism
memory management specifications
registers
Operand conventions
,
Operand placement and performance
,
Operating environment architecture (OEA)
Operations
bus operations caused by cache control instructions
,
instruction cache block fill
,
read operation
response to snooped bus transactions
,
single-beat write operations
Overview
P
Page address translation
definition
,
page address translation flow
,
page size
,
selection of page address translation
,
,
TLB organization
,
Page history status
cases of dcbt and dcbtst misses
R and C bit recording
Page table updates
,
Performance monitor
event counting
,
event selecting
performance monitor interrupt
performance monitor SPRs
,
purposes
registers
warnings
,
Physical address generation
,
Pipeline
instruction timing, definition
,
pipeline stages
pipelined execution unit
superscalar/pipeline diagram
,
PMC1 and PMC2 registers
PMCn (performance monitor counter) registers
Power and ground signals
,
Power management
doze mode
dynamic power management
,
full-power mode
,
nap mode
programmable power modes
sleep mode
software considerations
,
PowerPC architecture
operating environment architecture (OEA)
user instruction set architecture (UISA)
,
virtual environment architecture (VEA)
,
Priorities, exception
Process switching
,
Processor control instructions
,
,
Program exception
Program order, definition
Programmable power states
doze mode
nap mode
sleep mode
Protection of memory areas
no-execute protection
,
options available
protection violations
,
PVR (processor version register)
Q
QACK (quiescent acknowledge) signal
QREQ (quiescent request) signal
Qualified bus grant
Qualified data bus grant
,
R
Read operation
,
Read-atomic operation
,
Read-with-intent-to-modify operation
,
Real address (RA), see Physical address generation
Real addressing mode (translation disabled)
data accesses
,
instruction accesses
support for real addressing mode
,
Referenced (R) bit maintenance recording
,
,
,
Registers
implementation-specific
ICTC
,
L2CR
,
MMCR0
,
,
MMCR1
,
,
SIA
,
THRMn
UMMCR0
UMMCR1
UPMCn
USIA
,
performance monitor registers
,
SPR encodings
supervisor-level
BAT registers
,