IBM POWERPC 750GL - Manual (Page 3)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umTOC.fm.(1.2)
March 27, 2006
Page 3 of 377
List of Figures .............................................................................................................. 13
List of Tables ................................................................................................................ 15
About This Manual ........................................................................................................ 19
Who Should Read This Manual ............................................................................................................ 19
Related Publications ............................................................................................................................. 19
Conventions Used in This Manual ........................................................................................................ 20
Using This Manual with the Programming Environments Manual ......................................................... 22
1. PowerPC 750GX Overview ....................................................................................... 23
1.1 750GX Microprocessor Overview ................................................................................................... 23
1.2 750GX Microprocessor Features .................................................................................................... 25
1.2.1 Instruction Flow ..................................................................................................................... 29
1.2.1.1 Instruction Queue and Dispatch Unit .............................................................................. 29
1.2.1.2 Branch Processing Unit (BPU) ....................................................................................... 29
1.2.1.3 Completion Unit .............................................................................................................. 30
1.2.2 Independent Execution Units ................................................................................................. 31
1.2.2.1 Integer Units (IUs) .......................................................................................................... 31
1.2.2.2 Floating-Point Unit (FPU) ............................................................................................... 31
1.2.2.3 Load/Store Unit (LSU) .................................................................................................... 32
1.2.2.4 System Register Unit (SRU) ........................................................................................... 32
1.2.3 Memory Management Units (MMUs) ..................................................................................... 32
1.2.4 On-Chip Level 1 Instruction and Data Caches ...................................................................... 33
1.2.5 On-Chip Level 2 Cache Implementation ................................................................................ 35
1.2.6 System Interface/Bus Interface Unit (BIU) ............................................................................. 35
1.2.7 Signals ................................................................................................................................... 37
1.2.8 Signal Configuration .............................................................................................................. 38
1.2.9 Clocking ................................................................................................................................. 40
1.3 750GX Microprocessor Implementation .......................................................................................... 40
1.4 PowerPC Registers and Programming Model ................................................................................ 42
1.5 Instruction Set ................................................................................................................................. 45
1.5.1 PowerPC Instruction Set ....................................................................................................... 45
1.5.2 750GX Microprocessor Instruction Set .................................................................................. 47
1.6 On-Chip Cache Implementation ...................................................................................................... 47
1.6.1 PowerPC Cache Model ......................................................................................................... 47
1.6.2 750GX Microprocessor Cache Implementation .................................................................... 47
1.7 Exception Model .............................................................................................................................. 48
1.7.1 PowerPC Exception Model .................................................................................................... 48
1.7.2 750GX Microprocessor Exception Implementation ............................................................... 49
1.8 Memory Management ..................................................................................................................... 51
1.8.1 PowerPC Memory-Management Model ................................................................................ 51
1.8.2 750GX Microprocessor Memory-Management Implementation ........................................... 52
1.9 Instruction Timing ............................................................................................................................ 52
1.10 Power Management ...................................................................................................................... 54
1.11 Thermal Management ................................................................................................................... 55
1.12 Performance Monitor ..................................................................................................................... 56