IBM POWERPC 750GL - Manual (Page 375)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umIX.fm.(1.2)
March 27, 2006 Index
Page 375 of 377
Stall, definition , 211
Static branch prediction , 216 , 229
stwcx. , 162
Superscalar, definition , 211
sync
,
162
SYNC operation
,
143
Synchronization
context/execution synchronization , 90
execution of rfi , 161
memory synchronization instructions , 113 , 114
SYSCLK (system clock) signal
,
277
System call exception
,
171
System linkage instructions
,
108
,
118
System register unit
execution timing , 234
latency, CR logical instructions , 240
latency, system register instructions , 238
T
TA (transfer acknowledge) signal
,
268
Table search flow (primary and secondary)
,
204
TBL/TBU (time base lower and upper) registers , 60 , 62
TBST (transfer burst) signal , 259 , 294 , 303
TEA (transfer error acknowledge) signal , 269 , 307
Termination , 300 , 303
Thermal assist unit (TAU) , 343
Thermal management interrupt exception
,
174
THRMn (thermal management) registers
,
78
Throughput, definition , 211
Timing diagrams, interface
address transfer signals , 292
burst transfers with data delays , 314
single-beat reads
,
310
single-beat reads with data delays
,
312
single-beat writes
,
311
single-beat writes with data delays , 313
use of TEA , 315
using DBWO , 320
Timing, instruction
BPU execution timing
,
225
branch timing example
,
231
cache hit
,
220
cache miss , 223
execution unit , 225
FPU execution timing , 232
instruction dispatch , 224
instruction flow
,
215
instruction scheduling guidelines
,
236
IU execution timing , 232
latency summary , 238
load/store unit execution timing , 233
SRU execution timing , 234
stage, definition , 211
TLB
description , 199
invalidate (tlbie instruction) , 201 , 207
LRU replacement , 201
organization for ITLB and DTLB , 199
TLB miss and table search operation
,
200
,
204
TLB invalidate
description
,
201
TLB management instructions , 120
TLB miss, effect , 236
tlbie , 120
tlbsync
,
120
Transactions, data cache
,
140
Transfer
,
292
,
303
Trap instructions , 108
TS (transfer start) signal , 253 , 292
TSIZn (transfer size) signals , 258 , 294
TTn (transfer type) signals , 256 , 294
U, V, W
UMMCR0 (user monitor mode control register 0)
,
73
,
351
UMMCR1 (user monitor mode control register 1)
,
74
,
351
UPMCn (user performance monitor counter) registers ,
75 , 354
Use of TEA, timing , 315
User instruction set architecture (UISA)
description , 41
registers
,
59
USIA (user sampled instruction address) register
,
76
,
355
Using DBWO, timing , 320
Virtual environment architecture (VEA) , 41
WIMG bits , 308
Write-back, definition
,
211
Write-through mode (W bit)
cache interactions
,
125
Write-with-Atomic operation , 143
Write-with-Flush operation , 143
Write-with-Kill operation , 143
WT (write-through) signal , 260
X
XER register
,
59