IBM POWERPC 750GL - Manual (Page 202)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 202 of 377
gx_05.fm.(1.2)
March 27, 2006
Other than the possible TLB miss on the next instruction prefetch, the tlbie instruction does not affect the
instruction fetch operation—that is, the prefetch buffer is not purged and does not cause these instructions to
be refetched.
5.4.4 Page-Address-Translation Summary
Figure 5-8 on page 203 provides the detailed flow for the page-address-translation mechanism. The figure
includes the checking of the N bit in the segment descriptor and then expands on the ‘TLB Hit’ branch of
Figure 5-6 on page 191.
The detailed flow for the ‘TLB Miss’ branch of Figure 5-6 on page 191 is described in Section 5.4.5, Page
Table-Search Operation, on page 204.
Note: As in the case of block-address translation, if an attempt is made to execute a dcbz instruction to a
page marked either write-through or caching-inhibited (W = 1 or I = 1), an alignment exception is generated.
The checking of memory-protection violation conditions is described in Chapter 7, “Memory Management” in
the PowerPC Microprocessor Family: The Programming Environments Manual.