IBM POWERPC 750GL - Manual (Page 69)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006 Programming Model
Page 69 of 377
29 BHT
Branch history table enable
0 BHT disabled. The 750GX uses static branch prediction as defined by the
PowerPC User Instruction Set Architecture (UISA) for those branch instructions
the BHT would have otherwise used to predict (that is, those that use the CR as
the only mechanism to determine direction). For more information on static
branch prediction, see “Conditional Branch Control,” in Chapter 4 of the Pow-
erPC Microprocessor Family: The Programming Environments Manual.
1 Allows the use of the 512-entry branch history table (BHT).
The BHT is disabled at power-on reset. All entries are set to weakly, not-taken.
30 Reserved Reserved.
31 NOOPTI
No-op the data-cache touch instructions.
0 The Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store
(dcbtst) instructions are enabled.
1 The dcbt and dcbtst instructions are no-oped globally.
Bits Field Name Description
1. For additional information, see Section 11.9, Checkstops, on page 361.
2. For additional information about power-saving modes, see Table 10-2, HID0 Power Saving Mode Bit Settings, on page 337.