IBM POWERPC 750GL - Manual (Page 372)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Index
Page 372 of 377
750gx_umIX.fm.(1.2)
March 27, 2006
integer , 99
byte reverse instructions , 102
floating-point move , 98
floating-point store , 104
integer load
,
99
integer multiple
,
102
integer store
,
101
memory synchronization , 113 , 114
string instructions , 103
memory control instructions , 115 , 119
memory synchronization instructions
,
113
,
114
processor control instructions
,
108
,
113
,
118
reserved instructions
,
89
rfi , 161
stwcx. , 162
support for lwarx/stwcx. , 319
sync , 162
system linkage instructions , 108
tlbie
,
120
tlbsync
,
120
trap instructions
,
108
Integer arithmetic instructions , 92
Integer compare instructions , 93
Integer load instructions , 99
Integer logical instructions , 94
Integer rotate/shift instructions
,
95
Integer store gathering
,
234
Integer store instructions , 101
Integer unit execution timing , 232
Interrupt, external , 169
ISI exception , 169
isync, instruction synchronization
,
115
,
162
ITLB organization
,
200
Kill block operation
,
143
L
L2CR (L2 cache control register) , 81 , 329
Latency
load/store instructions , 244
Latency, definition
,
210
Load/store
address generation
,
99
byte reverse instructions , 102
execution timing , 233
floating-point load instructions , 104
floating-point move instructions , 98
floating-point store instructions
,
105
integer load instructions
,
99
integer store instructions , 101
latency, load/store instructions , 244
load/store multiple instructions , 102
string instructions , 103
Logical address translation , 179
LR (link register)
,
59
lwarx/stwcx. support , 319
M
Machine check exception , 167
MCP (machine check interrupt) signal , 62 , 152 , 271
MEI protocol
hardware considerations
,
128
read operations
,
140
state transitions , 147
Memory accesses , 282
Memory coherency bit (M bit)
cache interactions , 125
timing considerations
,
235
Memory control instructions
description , 115 , 119
Memory management unit
address translation flow , 189
address translation mechanisms , 186 , 189
block address translation
,
186
,
189
,
196
block diagrams
32-bit implementations
,
183
DMMU , 185
IMMU , 184
exceptions summary , 192
features summary , 180
implementation-specific features , 180
instructions and registers
,
194
memory protection
,
187
overview , 179
page address translation , 186 , 189 , 202
page history status , 188 , 196 – 199
real addressing mode , 189 , 195
segment model
,
196
Memory synchronization instructions
,
113
,
114
Misaligned data transfer
,
299
Misalignment
misaligned accesses , 82
MMCRn (monitor mode control registers) , 72 , 172 , 351
MSR (machine state register)
FE0/FE1 bits
,
160
IP bit
,
163
PM bit
,
60
RI bit , 161
settings due to exception , 162
Multiple-precision shifts , 95
N
No-DRTRY mode
,
318