IBM POWERPC 750GL - Manual (Page 265)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006 Signal Descriptions
Page 265 of 377
7.2.6.2 Data-Bus Write-Only (DBWO)
The data-bus write-only (DBWO) signal is an input-only signal on the 750GX.
7.2.6.3 Data Bus Busy (DBB)
The data bus busy (DBB) signal is both an input and output signal on the 750GX.
Data Bus Busy (DBB)—Output
Negated Indicates that the 750GX is not granted next data-bus ownership.
Timing Assertion Might occur on any cycle; not recognized until the cycle TS is asserted, or
later.
Negation Might occur on any cycle to indicate the 750GX cannot assume data-bus
ownership.
State Asserted If two or more data tenure requests are pending for the 750GX due to
address pipelining, indicates that the 750GX should run the data-bus tenure
for the next pipelined write transaction even if a read address tenure was
pipelined on the bus before the write address tenure. DBWO allows write
data tenures to be run ahead of read data tenures. However, it does not
allow write data tenures to be run ahead of other write data tenures. If no
write requests are pending, the 750GX will ignore DBWO and assume data-
bus ownership for the next pending read request.
Negated Indicates that the 750GX must run its read and write data-bus tenures in the
same order as their address tenures.
Timing Assertion/
Negation Sampled by the 750GX only on the clock that a qualified DBG is recognized.
Start-Up See Table 7-6, Summary of Mode Select Signals, on page 274 for a descrip-
tion of the start-up function.
State Asserted Indicates that the 750GX is the current data-bus owner. The 750GX will
always assume data-bus ownership if it needs the data bus and determines
a qualified data-bus grant (see DBG).
Negated Indicates that the 750GX is not the current data-bus owner, unless the data
retry (DRTRY) signal has extended the data tenure for the last or only data
beat.