IBM POWERPC 750GL - Manual (Page 180)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 180 of 377
gx_05.fm.(1.2)
March 27, 2006
Basic features of the 750GX MMU implementation defined by the OEA are as follows:
• Support for real-addressing mode—Effective-to-physical address translation can be disabled separately
for data and instruction accesses.
• Block-address translation—Each of the BAT array entries (eight IBAT entries and eight DBAT entries)
provides a mechanism for translating blocks as large as 256 MB from the 32-bit effective address space
into the physical memory space. This can be used for translating large address ranges whose mappings
do not change frequently.
• Segmented address translation—The 32-bit effective address is extended to a 52-bit virtual address by
substituting 24 bits of upper address bits from the segment register, for the 4 upper bits of the effective
address (EA), which are used as an index into the segment register file. This 52-bit virtual address space
is divided into 4-KB pages, each of which can be mapped to a physical page.
The 750GX also provides the following features that are not required by the PowerPC Architecture:
• Separate translation lookaside buffers (TLBs)—The 128-entry, 2-way set-associative instruction TLBs
(ITLBs) and data TLBs (DTLBs) keep recently-used page-address translations on-chip.
• Table-search operations performed in hardware—The 52-bit virtual address is formed and the MMU
attempts to fetch the page table entry (PTE), which contains the physical address, from the appropriate
TLB on-chip. If the translation is not found in a TLB (that is, a TLB miss occurs), the hardware performs a
table-search operation (using a hashing function) to search for the PTE.
• TLB invalidation— The 750GX implements the optional TLB Invalidate Entry (tlbie) and TLB Synchronize
(tlbsync) instructions, which can be used to invalidate TLB entries. For more information on the tlbie and
tlbsync instructions, see Section 5.4.3.2, TLB Invalidation, on page 201.
Figure 5-1 summarizes the 750GX MMU features, including those defined by the PowerPC Architecture
(OEA) for 32-bit processors and those specific to the 750GX.
Table 5-1. MMU Feature Summary (Page 1 of 2)
Feature Category
Architecturally Defined/
750GX-Specific
Feature
Address ranges Architecturally defined
2 32 bytes of effective address
2 52 bytes of virtual address
2 32 bytes of physical address
Page size Architecturally defined 4 KB
Segment size Architecturally defined 256 MB
Block-address translation Architecturally defined
Range of 128 KB–256 MB sizes
Implemented with IBAT and DBAT registers in BAT array
Memory protection Architecturally defined
Segments selectable as no-execute
Pages selectable as user/supervisor and read-only or guarded
Blocks selectable as user/supervisor and read-only or guarded
Page history Architecturally defined Referenced and changed bits defined and maintained
Page-address translation Architecturally defined
Translations stored as PTEs in hashed page tables in memory
Page table size determined by mask in SDR1 register