IBM POWERPC 750GL User Manual
IBM Computer Accessories
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Table of contents
Document Outline
- Title Page
- Copyright and Disclaimer
- List of Figures
- List of Tables
- About This Manual
- 1. PowerPC 750GX Overview
- 1.1 750GX Microprocessor Overview
- 1.2 750GX Microprocessor Features
- 1.3 750GX Microprocessor Implementation
- 1.4 PowerPC Registers and Programming Model
- 1.5 Instruction Set
- 1.6 On-Chip Cache Implementation
- 1.7 Exception Model
- 1.8 Memory Management
- 1.9 Instruction Timing
- 1.10 Power Management
- 1.11 Thermal Management
- 1.12 Performance Monitor
- 2. Programming Model
- 2.1 PowerPC 750GX Processor Register Set
- 2.2 Operand Conventions
- 2.3 Instruction Set Summary
- 3. Instruction-Cache and Data-Cache Operation
- 3.1 Data-Cache Organization
- 3.2 Instruction-Cache Organization
- 3.3 Memory and Cache Coherency
- 3.4 Cache Control
- 3.5 Cache Operations
- 3.6 L1 Caches and 60x Bus Transactions
- 3.7 MEI State Transactions
- 4. Exceptions
- 4.1 PowerPC 750GX Microprocessor Exceptions
- 4.2 Exception Recognition and Priorities
- 4.3 Exception Processing
- 4.4 Process Switching
- 4.5 Exception Definitions
- 4.5.1 System Reset Exception (0x00100)
- 4.5.2 Machine-Check Exception (0x00200)
- 4.5.3 DSI Exception (0x00300)
- 4.5.4 ISI Exception (0x00400)
- 4.5.5 External Interrupt Exception (0x00500)
- 4.5.6 Alignment Exception (0x00600)
- 4.5.7 Program Exception (0x00700)
- 4.5.8 Floating-Point Unavailable Exception (0x00800)
- 4.5.9 Decrementer Exception (0x00900)
- 4.5.10 System Call Exception (0x00C00)
- 4.5.11 Trace Exception (0x00D00)
- 4.5.12 Floating-Point Assist Exception (0x00E00)
- 4.5.13 Performance-Monitor Interrupt (0x00F00)
- 4.5.14 Instruction Address Breakpoint Exception (0x01300)
- 4.5.15 System Management Interrupt (0x01400)
- 4.5.16 Thermal-Management Interrupt Exception (0x01700)
- 4.5.17 Data Address Breakpoint Exception
- 4.5.18 Soft Stops
- 4.5.19 Exception Latencies
- 4.5.20 Summary of Front-End Exception Handling
- 4.5.21 Timer Facilities
- 4.5.22 External Access Instructions
- 5. Memory Management
- 5.1 MMU Overview
- 5.2 Real-Addressing Mode
- 5.3 Block-Address Translation
- 5.4 Memory Segment Model
- 6. Instruction Timing
- 6.1 Terminology and Conventions
- 6.2 Instruction Timing Overview
- 6.3 Timing Considerations
- 6.4 Execution-Unit Timings
- 6.4.1 Branch Processing Unit Execution Timing
- 6.4.2 Integer Unit Execution Timing
- 6.4.3 Floating-Point Unit Execution Timing
- 6.4.4 Effect of Floating-Point Exceptions on Performance
- 6.4.5 Load/Store Unit Execution Timing
- 6.4.6 Effect of Operand Placement on Performance
- 6.4.7 Integer Store Gathering
- 6.4.8 System Register Unit Execution Timing
- 6.5 Memory Performance Considerations
- 6.6 Instruction Scheduling Guidelines
- 6.7 Instruction Latency Summary
- 7. Signal Descriptions
- 7.1 Signal Configuration
- 7.2 Signal Descriptions
- 7.2.1 Address-Bus Arbitration Signals
- 7.2.2 Address Transfer Start Signals
- 7.2.3 Address Transfer Signals
- 7.2.4 Address Transfer Attribute Signals
- 7.2.5 Address Transfer Termination Signals
- 7.2.6 Data-Bus Arbitration Signals
- 7.2.7 Data-Transfer Signals
- 7.2.8 Data-Transfer Termination Signals
- 7.2.9 System Status Signals
- 7.2.10 Reset Signals
- 7.2.11 Processor Status Signals
- 7.2.12 Processor Mode Selection Signals
- 7.2.13 I/O Voltage Select Signals
- 7.2.14 Test Interface Signals
- 7.2.15 Clock Signals
- 7.2.16 Power and Ground Signals
- 8. Bus Interface Operation
- 9. L2 Cache
- 10. Power and Thermal Management
- 11. Performance Monitor and System Related Features
- 11.1 Performance-Monitor Interrupt
- 11.2 Special-Purpose Registers Used by Performance Monitor
- 11.2.1 Performance-Monitor Registers
- 11.2.1.1 Monitor Mode Control Register 0 (MMCR0)
- 11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0)
- 11.2.1.3 Monitor Mode Control Register 1 (MMCR1)
- 11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)
- 11.2.1.5 Performance-Monitor Counter Registers (PMCn)
- 11.2.1.6 User Performance-Monitor Counter Registers (UPMC1-UPMC4)
- 11.2.1.7 Sampled Instruction Address Register (SIA)
- 11.2.1.8 User Sampled Instruction Address Register (USIA)
- 11.2.1 Performance-Monitor Registers
- 11.3 Event Counting
- 11.4 Event Selection
- 11.5 Notes
- 11.6 Debug Support
- 11.7 JTAG/COP Functions
- 11.8 Resets
- 11.9 Checkstops
- 11.10 750GX Parity
- Acronyms and Abbreviations
- Index
- Revision Log