Intel 41210 - Manual (Page 64)

64 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Design Guide Checklist
Table 24. JTAG Signals
Signal Recommendations Reason/Impact
TCK If not used for JTAG, leave as No Connect Internal pull-up
TDI If not used for JTAG, leave as No Connect Internal pull-up
TDO If not used for JTAG, leave as No Connect Internal pull-up
TMS If not used for JTAG, leave as No Connect Internal pull-up
TRST# Connect to ground via a 1K
Ω
pulldown resistor.
If TAP interface is not used this
should be tied to ground.