Intel 41210 - Manual (Page 54)

54 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Circuit Implementations
10.2.1 SM Bus
The SMBus interface does not have configuration registers. The SMBus address is set by the states
of pins SMBUS[5] and SMBUS [3:1] when PERST# is asserted as described in
Table 17 .
Refer to Section 2.4 for details on how to use the SMBus to initialize 41210 Bridge registers with a
microcontroller.
Table 17. SMBUs Address Configuration
Bit Value
7 1
6 1
5 SMBUS[5]
4 0
3 SMBUS[3]
2 SMBUS[2]
1 SMBUS[1]