Motorola TMS320C6711D User Manual

Motorola Hardware

Table of contents

Document Outline

SPRS292A - TMS320C6711D
features
Table of Contents
REVISION HISTORY
GDP and ZDP BGA packages (bottom view)
description
device characteristics
device compatibility
functional block and CPU (DSP core) diagram
CPU (DSP core) description
memory map summary
peripheral register descriptions
signal groups description
DEVICE CONFIGURATIONS
- device configurations at device reset
- DEVCFG register description
TERMINAL FUNCTIONS
- Terminal Functions
development support
- Software Development Tools:
- Hardware Development Tools:
device support
- device and development-support tool nomenclature
  - TMX
  - TMP
  - TMS
  - TMDX
  - TMDS
- documentation support
CPU CSR register description
cache configuration (CCFG) register description
interrupt sources and interrupt selector
EDMA module and EDMA selector
- ESEL0 Register (0x01A0 FF00)
- ESEL1 Register (0x01A0 FF04)
- ESEL3 Register (0x01A0 FF0C)
PLL and PLL controller
- PLLCSR Register (0x01B7 C100)
- PLLM Register (0x01B7 C110)
- PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers
- OSCDIV1 Register (0x01B7 C124)
general-purpose input/output (GPIO)
power-down mode logic
- triggering, wake-up, and effects
power-supply sequencing
- system-level design considerations
- power-supply design considerations
power-supply decoupling
IEEE 1149.1 JTAG compatibility statement
EMIF device speed
EMIF big endian mode correctness
bootmode
reset
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
recommended operating conditions‡
electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)
PARAMETER MEASUREMENT INFORMATION
- signal transition levels
- AC transient rise/fall time specifications
- timing parameters and board routing analysis
INPUT AND OUTPUT CLOCKS
- timing requirements for CLKIN†‡§ (see Figure 22)
- timing requirements for CLKIN†‡§ (see Figure 22)
- switching characteristics over recommended operating conditions for CLKOUT2†‡ ( see Figure 23)
- switching characteristics over recommended operating conditions for CLKOUT3†§ (see Figure 24)
- timing requirements for ECLKIN† (see Figure 25)
- switching characteristics over recommended operating conditions for ECLKOUT‡§¶ (see Figure 26)
ASYNCHRONOUS MEMORY TIMING
- timing requirements for asynchronous memory cycles†‡§ (see Figure 27-Figure 28)
- switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§ (see Figure 27–Figure 28)
SYNCHRONOUS-BURST MEMORY TIMING
- timing requirements for synchronous-burst SRAM cycles† (see Figure 29)
- switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ ( see Figure 29 and Figure 30)
SYNCHRONOUS DRAM TIMING
- timing requirements for synchronous DRAM cycles† (see Figure 31)
- switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ ( see Figure 31- Figure 37)
HOLD\/HOLDA\ TIMING
- timing requirements for the HOLD\/HOLDA\ cycles† (see Figure 38)
- switching characteristics over recommended operating conditions for the HOLD\/HOLDA\ cycles†‡ ( see Figure 38)
BUSREQ TIMING
- switching characteristics over recommended operating conditions for the BUSREQ cycles ( see Figure 39)
RESET TIMING
- timing requirements for reset†‡ (see Figure 40)
- switching characteristics over recommended operating conditions during reset¶ (see Figure 40)
EXTERNAL INTERRUPT TIMING
- timing requirements for external interrupts† (see Figure 41)
HOST-PORT INTERFACE TIMING
- timing requirements for host-port interface cycles†‡ (see Figure 42, Figure 43, Figure 44, and Figure 45)
- switching characteristics over recommended operating conditions during host-port interface cycles†‡ ( see Figure 42, Figure 43, Figure 44, and Figure 45)
MULTICHANNEL BUFFERED SERIAL PORT TIMING
- timing requirements for McBSP†‡ (see Figure 46)
- switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46)
- timing requirements for FSR when GSYNC = 1 (see Figure 47)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 48)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 48)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 49)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 49)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 50)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 51)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 51)
TIMER TIMING
- timing requirements for timer inputs† (see Figure 52)
- switching characteristics over recommended operating conditions for timer outputs† ( see Figure 52)
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
- timing requirements for GPIO inputs†‡ (see Figure 53)
- switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 53)
JTAG TEST-PORT TIMING
- timing requirements for JTAG test port (see Figure 54)
- switching characteristics over recommended operating conditions for JTAG test port ( see Figure 54)
MECHANICAL DATA
- package thermal resistance characteristics
- thermal resistance characteristics (S-PBGA package) for GDP
- thermal resistance characteristics (S-PBGA package) for ZDP
- packaging information