Avago Technologies LSI21040 - Manual (Page 56)

3.75 pc 10.25 pc 11.25 pc 38.25 pc
4.333 pc
48.583 pc
52.5 pc
34.5 pc
44.25 pc
A-2 Glossary of Terms and Abbreviations
Bus Mastering A high-performance way to transfer data. The host adapter controls the
transfer of data directly to and from system memory without interrupting
the computer’s microprocessor. This is the fastest way for multitasking
operating systems to transfer data.
Byte A unit of information consisting of eight bits.
CISPR A special international committee on radio interference (Committee,
International and Special, for Protection in Radio).
Configuration Refers to the way a computer is set up; the combined hardware
components (computer, monitor, keyboard, and peripheral devices) that
make up a computer system; or the software settings that allow the
hardware components to communicate with each other.
CPU Central Processing Unit. The “brain” of the computer that performs the
actual computations. The term Microprocessor Unit (MPU) is also used.
CRC Cyclic Redundancy Check is an error detection code used in Ultra160
SCSI. Four bytes are transferred with the data to increase the reliability
of data transfers. CRC is used on the Double Transition (DT) Data-In and
DT Data-Out phases.
Device Driver A program that allows a microprocessor (through the operating system)
to direct the operation of a peripheral device.
DMA Direct Memory Access.
Differential SCSI A hardware configuration for connecting SCSI devices. It uses a pair of
lines for each signal transfer (as opposed to Single-Ended SCSI which
references each SCSI signal to a common ground).
DMA Bus
Master A feature that allows a peripheral to control the flow of data to and from
system memory by blocks, as opposed to PIO (Programmed I/O) where
the processor is in control and the flow is by byte.
Domain
Validation Domain Validation is a software procedure in which a host queries a
device to determine its ability to communicate at the negotiated Ultra160
data rate.
DT Clocking In Double Transition (DT) Clocking data is sampled on both the asserting
and deasserting edge of the REQ/ACK signal. DT clocking may only be
implemented on an LVD SCSI bus.