Avago Technologies LSI21040 - Manual (Page 13)

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Features 1-3
– Supports dual address cycle generation for all SCRIPTS
– Presents a single electrical load to the PCI Bus (True PCI
Multifunction Device)
•
Bursts 2 to 128 Dwords across the PCI bus
•
Supports 32-bit or 64-bit word data bursts with variable burst lengths
•
Supports the PCI Cache Line Size register
•
Prefetches up to 8 Dwords of SCRIPTS instructions
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands
•
Bursts SCRIPTS opcode fetches across the PCI bus
•
Supports universal 3.3 V and 5 V PCI signaling environment
1.2.2 SCSI Interface
The SCSI interface on the LSI21040 operates as an 8-bit or 16-bit
interface. It supports 8-bit or 16-bit, synchronous and asynchronous, LVD
or SE, Fast, Ultra, Ultra2, and Ultra160 SCSI protocols in various
combinations.
The LSI53C1010 contains the SCSI functionality for the LSI21040. This
chip is a PCI to Ultra160 SCSI Controller with LVD Link™ Universal
Transceivers. It connects directly to the SCSI bus and generates signal
timing and bus protocol in compliance with SCSI standards.
The SCSI interface includes these features:
•
Performs wide, Ultra160 SCSI synchronous data transfers as fast as
160 Mbytes/s using Double Transition (DT) clocking for Channel A
•
Performs wide, Ultra SCSI SE synchronous transfers as fast as
40 Mbytes/s for Channel B
•
Enables LVD or SE termination on Channel A automatically
•
Enables SE termination on Channel B automatically
•
Contains internal 68-pin high density connectors for Channel A and
Channel B
•
Contains internal ribbon connector 50-pin for Channel B
•
Contains external connector 68-pin high density for Channel A