Avago Technologies MegaRAID SAS 8204ELP - Manual (Page 20)

1-6 Overview
Copyright © 2007 by LSI Corporation. All rights reserved.
through in-band, SCSI-enclosed storage. The configuration must
support STP and SMP.
Figure 1.1 shows a direct-connect configuration. The Inter-IC (I
2
C)
interface communicates with peripherals. The external memory bus
provides a 32-bit memory bus, parity checking, and chip select signals
for pipelined synchronous burst static random access memory
(PSBRAM), nonvolatile static random access memory (NVSRAM), and
Flash ROM.
Note: The external memory bus is 32-bit for the SAS 8704ELP
and the SAS 8708ELP, and 64-bit for the SAS 8708EM2,
the SAS 8880EM2, and the SAS 8888ELP.
Figure 1.1 Example of an LSI SAS Direct-Connect Application
Figure 1.2 shows an example of a SAS RAID controller configured with
an LSISASx12 expander that is connected to SAS disks, SATA II disks,
or both.
Flash ROM/ SAS
PCI Express
RAID Controller
SAS/SATA II Device
32-Bit Memory
Address/Data
Bus
PSBRAM/
I
2
C
SAS/SATA II Device
SAS/SATA II Device
SAS/SATA II Device
PCI Express Interface
NVSRAM
I 2 C
Interface