Grass Valley 8950ADC - Manual (Page 40)

40 8950ADC Instruction Manual
Functional Description
Input Buffers/Amplifiers/Low Pass Filters
Three-channel input Clamping Video Amplifiers support the professional
studio TV standard with 20 MHz bandwidth and > 60dB signal to noise
ratio. Black level voltage is under CPU control (DC feedback D/A con-
verters). Signals are passed from the amplifiers to three identical Low Pass
Filters (LPF), where all spectral components above 15 MHz are removed
from incoming signals.
Analog to Digital Converters
The three 10-bit ADCs have a 54 MHz sampling rate, and perform high
speed analog to digital conversion on the signals received from the LPFs.
Digital Signal Processor FPGA
The DSP FPGA performs the following signal processing:
• Input Signal Processor
After analog to digital conversion, the digitized video signal passes
through the Digital Input Signal Processor. This controls the gain of all
three input signals individually in the range of ± 15%. User input gain
control is also available through Embedded Processor. The clipping
circuit preludes overshooting errors in cases where either the input
signal level or amplifier gain is too high.
• Color Space Converter
The 8950ADC supports Y, (B-Y), (R-Y) or GBR input, and the Color
Space Converter automatically connects to the appropriate signal path.
The Color Space Converter converts an incoming GBR signal to Y,
(B-Y), (R-Y) according to the D1 Color space matrix.
• Sync Processor
The Sync Processor contains the H&V Extractor, Frame Pulse Extractor,
Standard Detector, and PLL Phase Detector Input Signal. (The Analog
Sync Separator and PLL Phase Detector are not part of the FPGA.)
• Filters and Decimators
The DSP FPGA performs Low Pass filtering (6 MHz bandwidth) and
decimation by 4 for all three channels. For the B-Y and R-Y channels the
DSP FPGA performs additional Low Pass filtering and decimation by 2
(3 MHz bandwidth).
• Control
The Control FPGA contains parallel communication blocks between
the embedded processor and FPGA.