Verilink AS4000 (34-00244) Product Manual - Manual (Page 125)

Test Access Module (TAM)
Verilink AS4000 User Manual 8-3
Data The options are Normal or Inverted. Inverted causes ones to be sent as zeros and zeros
to be sent as ones. This might be done in an effort to increase the ones density of a
signal. This option must be set the same at both ends of a circuit.
Clock Initially choose Normal. If frequent errors occur at the port, try Inverted and check
performance of received data at the far end.
Normally, the down-going clock edge is in the middle of each bit. On lengthy cables
when a clock is sent from one device to clock data from the other device, the data arrives
skewed from the originating clock due to the round trip cable delay. When the delay is
such that the originating clock down-going edge is on the edge of the bit returned,
Inverted will correct this condition.
Interface The interface options are V.35, RS 530/422 and RS-232.
V.54 Loop The TAM card does not respond to the V.54 loop.