Measurement Computing CIO-QUAD0x User Manual

Page 16

4.3.2 Base +9: Input Signal Control Register

Controls Counter Cascading: (Non-quadrature mode)

Set the FLGx pin for the CARRY/BORROW function through the IOR Register bits 3 and 4 so that the cascaded direction
output will be CARRY for UP counting and BORROW for DOWN counting.

0, 1

(1) 96-bit counter (1-2-3-4)

0, 1

(1) 24-bit and (1) 72-bit counter (1/2-3-4)

1, 0

(2) 48-bit counters (1-2/3-4)

0, 0

(4) 24-bit counters (1/2/3/4)

PH4B1/PH4B0

PH4A

PH3B

PH3A

PH2B

PH2A

Defaults to 0x00 (four 24-bit counters; no inter-counter connections).

4.3.3 Base +10 and 11: Programmable Interrupt Controller Registers

The CIO-QUAD uses an 8259A Programmable Interrupt Controller which routes up to eight interrupts from the Index
inputs or Carry/Borrow outputs (due to overflow, underflow, or compare match, depending on strap setting and register
programming) from the LS7266's. The interrupt output from the 8259 is routed through the FPGA and register enabled and
set to IRQ 2, 3, 5, 7, 10, 11, 12, or 15 on the PC bus. Each interrupt can be masked to prevent unwanted interrupt
generation through 8259 programming.

The 8259A can only be used in non-vectored x86/x88 mode, or polled mode. That is, when an interrupt is generated, the
user must poll the 8259A to determine which interrupt was set. This mode is set externally to the PIC through the
folllowing hardware settings:

INTA* (pin 26) connected to +5V
SP\EN (pin 16) connected to 10kohm pullup to +5
CAS0:2 (pins 12,13,15) connected to 10kohm pullup to +5

For programming and further information on the 8259A interrupt controller, consult an Intel Peripheral Components data
book (or Harris 8259A data sheet).

int EXTCCONV cbQLoad(UBYTE ChanNum, long Preset)

This function is used to preset the counter for the specified channel. The preset count is copied to the register, and then the
preset is moved to the counter using the RLD register move preset to counter operation.

int EXTCCONV cbQGetStatus(UBYTE ChanNum, UBYTE *Flags)

The current status register is returned in Flags.

4.3.4 Base +12: Interrupt Select Register

Interrupt routing to PC-bus:

Interrupt Enable (INTE) = 1, Disable = 0

Interrupt Selection:

1, 1, 1

IRQ15

0, 1, 1

IRQ7

1, 1, 0

IRQ12

0, 1, 0

IRQ5

1, 0, 1

IRQ11

0, 0, 1

IRQ3

1, 0, 0

IRQ10

0, 0, 0

IRQ2

INT2, 1, 0

Interrupt

INT2, 1, 0

Interrupt