Measurement Computing PCI-DAS6023 - Manual (Page 24)

PCI-DAS6023 and PCI-DAS6025 User's Guide Functional Details
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A/D CONVERT signal
The A/D CONVERT signal indicates the start of an A/D conversion. It is available through software selection
as an input to any of the AUXIN pins (defaulting to AUXIN0) or the DAQ-Sync "DS A/D CONVERT" input
and as an output to any of the AUXOUT pins.
When used as an input, the polarity is software selectable. The A/D CONVERT signal starts an acquisition on
the selected edge. The convert pulses must be separated by a minimum of 5 s to remain within the 200 kS/s
conversion rate specification.
Refer back to Figure 6 and Figure 9 for the relationship of A/D CONVERT to the DAQ sequence. Figure 14
and Figure 15 show the input and output pulse width requirements for the A/D CONVERT signal.
Figure 14. A/D CONVERT signal input timing requirement
Figure 15. A/D CONVERT signal output timing requirement
The A/D CONVERT signal is generated by the on-board pacer circuit unless the external clock option is in use.
This signal may be gated by external hardware (A/D PACER GATE) or internally via software.
A/D PACER GATE signal
The A/D PACER GATE signal is used to disable scans temporarily. This signal may be programmed for input
at any of the AUXIN pins.
If the A/D PACER GATE signal is active, no scans can occur. If the A/D PACER GATE signal becomes active
during a scan in progress, the current scan is completed and scans are then held off until the gate is de-asserted.
A/D EXTERNAL TIME BASE signal
The A/D EXTERNAL TIME BASE signal can serve as the source for the on-board pacer circuit rather than
using the 40 MHz internal time base. Any AUXIN pin can be set programmatically as the source for this signal.
The polarity is programmable.
The maximum frequency for the A/D EXTERNAL TIME BASE signal is 20 MHz. The minimum pulse width
is 23 ns high or low. There is no minimum frequency specification.
Figure 16 shows the timing specifications for the A/D EXTERNAL TIME BASE signal.
t
w
= 37.5 ns minimum